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tle7259g lin transceiver data sheet, rev 2.1, april 2007 automotive power
p-dso-8 type package marking tle7259g p-dso-8 7259g data sheet 2 rev 2.1, 2007-04-27 lin transceiver tle7259g 1overview features ? transmission rate up to 20 kbaud ? compliant to lin specificat ion 1.2, 1.3, 2.0 and 2.1 ? support of k-line function (iso 9141) ? very high esd robustness ? very low electromagnetic emission (eme) ? very high electromagnetic immunity (emi) ? very low current consumption in sleep mode ? very low leakage current on the bus output ? control output for voltage regulator ? wake up source recognition (local/remote) ? for 3.3 v and 5 v micro controller i/o ? suitable for 12v and 24v board-net ? bus short to v bat protection ? bus short to gnd handling ? over temperature protection ? aec qualified description the tle7259g is a transceiver for the local interconnect network (lin) with integrated wake-up and protection features. it is designed for in-vehicle networks using data transmission rates from 2.4 kbaud to 20 kbaud. the tle7259g functions as a bus driver be tween the protocol controller and the physical bus inside the lin network. compliant to all lin standards and with a wide operational supply range the tle7259g can be used in all automotive applications. different operation modes and the inh output allow th e tle7259g to control external components, like voltage regulators. in sleep-mode the tle7259g draws less than 8 a of quiescent while still be ing able to wake up off of lin bus traffic and a local wake-up input. the very low leakage current on the bus pin makes the tle7259g especially suitable for ?mixed power supply? applications and supports the low quiescent current requirements of the lin network. based on the infineon smart power technology spt ? , the tle7259g provides excellent esd robustness together with a very high electromagnetic immunity (emi). the tle7259g reaches a very low level of electromagnetic emission (eme) within a broad frequenc y range and independent form the battery voltage. the infineon smart power technology spt ? allows bipolar and cmos control circuitry in accordance with dmos power devices existing on the same monolithi c circuit. the tle7259g and the infineon spt ? technology are aec qualified and tailored to withstand the harsh condition of the automotive environment.
tle7259g block diagram data sheet 3 rev 2.1, 2007-04-27 2 block diagram figure 1 functional block diagram local-wake and bus-wake comparator driver temp.- protection current limit output stage supply txd input mode control receiver rxd 1 filter 6 bus txd 4 en 2 inh 8 7 v s r bus filter r en r td timeout 3 wk gnd 5 5 v
data sheet 4 rev 2.1, 2007-04-27 tle7259g pin configuration 3 pin configuration 3.1 pin assignment figure 2 pin configuration (top view) 3.2 pin definitions and functions table 1 pin definitions and functions pin no. symbol function 1rxd receive data output; external pull up necessary low in dominant state, active low after a wake-up event at bus or wk pin 2en enable input; integrated pull-down, device in normal operation mode when high 3wk wake input; active low, negative edge triggered, internal pull-up 4txd transmit data input; integrated pull-down, low in dominant stat e; active low after wake-up via wk pin 5gnd ground 6bus bus output/input; lin bus line input/output low in dominant state internal pull-up 7 v s battery supply input 8inh inhibit output; battery supply related output high ( v s ) in normal and stand-by operation mode can be used to control an external voltage regulator can be used to control external bus termination resistor when the device will be used as master node rxd 1 2 3 45 6 7 8 en wk txd inh v s bus gnd
tle7259g functional description data sheet 5 rev 2.1, 2007-04-27 4 functional description the lin bus is a single wire, bi-directional bus, used fo r in-vehicle networks. the lin transceiver tle7259g is the interface between the micro controller and the physical lin bus (see figure 11 and figure 12 ). the logical values of the micro controller are driven to the lin bu s via the txd input of the tle7259g. the transmit data stream on the txd input is converted to a lin bus signal with optimized slew rate to minimize the eme level on the lin bus. the rxd output reads back the information from the lin bus to the micro controller, regardless of the logical value of the txd input. the rece iver has an integrated filter network to suppress noise on the lin bus and to increase the emi level of the transceiver. two logical states are possible on the lin bus according to the lin specification 2.1. the dominate state (voltage near gr ound) on the lin bus represents a ?logic 0? on the txd input of the tle7259g; the recessive state (voltage near supply voltage v s ) represents a ?logic 1? on the txd input (see timing diagram figure 9 ). every lin network consists of a master node and one or more slave nodes. to configure the tle7259g for master node applications, a resist or in the range of 1 k ? and a reverse diode must be connected between the lin bus and the power supply v s or the inh pin of the tle7259g (see figure 11 and figure 12 ). 4.1 operating modes the tle7259g has 3 different operation modes. after a power-up event the tle7259g starts from the stand-by mode. by setting the en pin to ?logic 1? the micro co ntroller can change the mode into normal-operation mode. figure 3 operation mode state diagram aea03514.vsd power-up wake up via bus: t > t wake,bus via wake: t > t wake 1) after wake up (via bus or wake) 2) after start up 3) after wake up via wake (internal strong pull down, > 1.9 ma) 4) after wake up via bus (internal weak pull down, 350 k ? ) en normal mode high high inh en sleep mode low floating inh stand-by inh en rxd txd low low 1) floating 2) low 3) high 4) high en high low en high en
data sheet 6 rev 2.1, 2007-04-27 tle7259g functional description 4.2 normal operation mode the tle7259g enters the normal mode after the micro controller sets en = high (see figure 3 ). in normal operation mode the lin bus receiver and the lin bus transmitter are active. data from the micro controller is transmitted to the lin bus via the txd pin, the receiver detects the data stream on the lin bus and outputs it to the rxd pin. 4.3 stand-by mode the stand-by mode is entered automatically after: ? a power-up event on the supply v s . ? a wake-up event on the lin bus. ? a local wake-up event on the pin wk. ? a power on reset caused by power supply v s dropping below v s,uv,pon ( v s < v s,uv,pon ). in stand-by mode no communication on the lin bus is po ssible. the output stage is disabled and the lin bus termination remains activated. the rxd and txd pins ar e indicating the wake-up source. the rxd pin remains ?low? after a local and bus wake-up event. a power-up event is indicated by a logical ?high? on rxd pin. the signal on the txd pin indicates the wake-up source, a weak pu ll-down signals a bus wake-up event and a strong pull- down signals a local wake-up event caused by the wk pin (see table 2 ). in order to detect a wake-up event via the txd pin, the external micro contro ller needs outputs needs to provide a lo gical ?high? signal. the wake-up flags indicating the wake-up source on the pins txd and rx d are reset by changing the operation mode to normal operation. the signal on the en pin remains ?low? due to an internal pull-down resistor. setting th e en pin to ?high?, by the micro controller the device returns to normal operation mode. entering the stand-by mode switches the inh output to v s . depending on the operation mode of the tle7259g external circuitry, like a voltage regulator, can be controlled by the inh output. table 2 operating modes mode en inh txd rxd lin bus termination comments sleep low floating low high 1) 1) pull-up resistor to micro controller power supply ( v io ) required (see figure 11 and figure 12 ). high impedance no wake-up request detected stand-by low high low 2) high 3) low high 1) 30 k ? (typical) rxd ?low? after local or bus wake-up rxd ?high? a fter power-up txd strong pull down after local wake-up (wk pin) 2) txd weak pull down after bus wake-up or power- up 3) 2) txd indicates logical ?low? in case the micro controller output is set to ?high? and the micro controller output current is limited to less than 1.9 ma. 3) txd indicates logical ?high? in case the micro controller output is set to ?high?. normal high high low high low high 30 k ? (typical) rxd reflects the signal on the lin bus txd driven by the micro controller
tle7259g functional description data sheet 7 rev 2.1, 2007-04-27 4.4 sleep mode in order to reduce the current consumption the tle72 59g offers a sleep mode. in sleep mode the quiescent current on v s and the leakage current on the pin bus, are cut back to a minimum. switching the tle7259g from normal operation mode to sleep mode, the en pin needs to be set to ?low?. a logical ?high? on the en pin sets the device direct back to normal operation mode (see figure 3 ). while the tle7259g is in sleep mode the following functions are available: ? the output stage is disabled and the internal bus term ination is switched off (high impedance on the bus pin). an internal current source on the bus pin ensures that the level on the bus pin re mains dominate and protects the lin network against accidental bus wake-up events. ? the receiver is turned off ? rxd and txd pins are disabled. the l ogical state on the txd pin is low, due to the internal pull-down resistor. the rxd pin is ?high? driven by the external pull-up resistor ? the inh output is switched off and floating. ? the bus wake-up comparator is active and turns the tl e7259g to stand-by mode in case of a bus wake-up. ? the wk pin is active and turns the tle7259g to stand-by mode in case of a local wake-up. ? the en pin remains active, switching en pin to ?hi gh? changes the operation mode to normal operation. 4.5 wake-up events there are 3 different ways to wake-up the tle7259g from sleep mode. ? bus or also called remote wake-up via a dominate signal on the lin bus. ? local wake-up via a minimum dominant time ( t wk ) on the wk pin. ? mode change from sleep mode to normal operation mode, by setting en pin to logical ?high?.
data sheet 8 rev 2.1, 2007-04-27 tle7259g functional description 4.6 bus wake-up figure 4 bus wake-up behavior the bus wake-up, often called remote wake-up, changes th e operation mode from sleep mode to stand-by mode. a falling edge on the lin bus, follow ed by a dominate bus signal t > t wk,bus results in a bus wake-up. the mode change to stand-by mode becomes active with the followi ng rising edge on the lin bus. the tle7259g remains in sleep mode until it detects a change from dominate to recessive on the lin bus (see figure 4 ). in stand-by mode the txd pin indicates the source of the wake-up event. a weak pull-down on the pin txd indicates a bus wake-up event (see figure 3 ). the rxd pin signals if a wake-u p event occurred or the power-up event. a logical ?low? on the rxd pin reports a local or bu s wake-up event, a logical ?high? signal on rxd indicates a power-up event. v bus v bus,dom v bus,wk lin bus signal sleep mode stand-by mode inh t wk,bus
tle7259g functional description data sheet 9 rev 2.1, 2007-04-27 4.7 local wake-up figure 5 local wake-up behavior beside the remote wake-up, a wake-up of the tle7259g vi a the wk pin is possible. this wake-up event is called local wake up. a falling edge on the wk pin followed by a logical ?low? for t > t wk results in a local wake up (see figure 5 ) and change the operation mode to stand-by mode. in stand-by mode the txd pin indicates the source of the wake-up event. a strong pull down on the pin txd indicates a local wake-up event via the pin wk (see figure 3 ). the rxd pin signals if a wake-up event occurred or the power-up event. a logical ?low? on the rxd pin repo rts a local or bus wake-up event, a logical ?high? signal on rxd indicates a power-up event. v wk v wk,l wk signal sleep mode stand-by mode inh t wk
data sheet 10 rev 2.1, 2007-04-27 tle7259g functional description 4.8 mode transition via en pin figure 6 mode transition via en pin it is also possible to change from sleep mode to normal operation mode by setting the en pin to logical ?low?.this feature is useful if the external micro controller is co ntinuously powered and not connected to the inh pin. the en pin has an integrate pull-down resistor to ensure the devi ce remains in sleep or stand-by mode even if the voltage on the en pin is floating. the en pin has an integrated hysteresis (see figure 6 ). a transition from logical ?high? to logical ?low? on the en pin changes the operation mode from normal operation mode to sleep mode. if the tle7259g is already in slee p mode, changing the en from ?low? to ?high? results into a mode change from sleep mode to normal operation m ode. if the device is in stand-by mode a change from ?low? to ?high? on the en pin changes the mode to normal operation mode (see figure 3 ). v en en signal v en,off sleep mode / stand-by mode t snorm v en,on en hysteresis sleep mode normal operation mode t nsleep
tle7259g functional description data sheet 11 rev 2.1, 2007-04-27 4.9 power-on reset figure 7 power-on reset and undervoltage situation a drooping power supply v s on a local ecu can effect the communication of the whole lin network. to avoid any blocking of the lin network by a local ecu the tle 7259g has an integrated power-on reset and undervoltage detection. in case the supply voltage is dropping below the power on reset level v s < v s,uv,pon , the tle7259g changes the operation mode to stand-by mode. in stand-b y mode the output stage of the tle7259g is disabled and no communication to the lin bus is possible. the inte rnal bus termination remains active as well as the inh pin (see figure 7 ). in stand-by mode the rxd pin signals the low power supply condition with a logical ?high? signal. a logical ?high? on the en pin changes the operation mode back to normal operation mode. in case the supply voltage v s is dropping below the specified operation range (see table 5 ), the tle7259g disables the output and receiver stage s. the feature secures the communication on the lin bus, even if the local ecu power supply of the tle7259g drops below the spec ified operating range. if the power supply reaches a higher level as the undervoltage level v s > v s,uv,pon the tle7259g continues with normal operation. a mode change only apply if the power supply v s drops below the power on reset level ( v s < v s,uv,pon ). 6xsso\yrowdjh9v 3rzhurquhvhwohyho 9 689321 5hvhwghylfhvhwwr6wdqg%\0rgh 3rzhurquhvhw 1rupdorshudwlrq prgh 5hvhwdqg &rppxqlfdwlrq eorfnhg 6wdqg%\ prgh %odqnlqjwlph w eodqn89 6xsso\yrowdjh9v 3rzhurquhvhwohyho 9 689321 1rupdorshudwlrq prgh &rppxqlfdwlrq eorfnhg %odqnlqjwlph w eodqn89 8qghuyrowdjhohyho 9 689%/. 1rupdorshudwlrq prgh
data sheet 12 rev 2.1, 2007-04-27 tle7259g functional description 4.10 txd time out function if the txd signal is dominant for a time t > t timeout the txd time-out function deacti vates the transmission of the lin signal to the bus. this is realized to prevent the bus from being permanently blocked by a permanent ?low? signal on the txd pin due to an error. the transmission is released again, after a rising edge at txd has been detected. 4.11 over temperature protection the tle7259g has an integrated over temperature sensor, to protect the device against thermal overstress. in case of an over temperatur e event, the temperat ure sensor will disable the output stage. an over temperature event will not cause any mode ch ange nor will it be signaled by either the rxd pin or the txd pin. when the junction temperature falls below the thermal shut down level t j < t jsd , the output stage is re-enabled and data communication can start again. a10c hysteresis avoids toggling during t he temperature shut down. 4.12 3.3 v and 5 v logic capability the tle7259g can be used for 3.3 v and 5 v micro controllers. the inputs (txd, en) take the reference voltage from the connected micro controller pins. the rxd output must have an external pull- up resistor to the micro controller supply, to define the output voltage level. 4.13 bus short to gnd feature the tle7259g has a feature implemented to protect the battery from running out of charge in the case the lin bus is shorted to gnd. in this failure case a norma l master term ination, a 1 k ? resistor and a diode connected between the bus pin and the power supply v s , would cause a constant current between v s and gnd, even in sleep mode. the resulting resistance between v s and gnd of this lin bus sh ort to gnd is lower than 1 k ? . to avoid this current during a generator off state, like in a parked car, the tle7259g has a bus short to gnd feature implemented. this feature is only applicable, if the master termination is connected to the i nh pin, instead of the v s power supply (see figure 11 and figure 12 ). in sleep mode the inh pin is switched of and no currently can flow between v s and gnd. the internal 30 k ? bus termination is al so switched off (see figure 1 and table 2 ) to minimize the discharge current. 4.14 lin specifications 1. 2, 1.3, 2.0 and 2.1 the device fulfills the physical layer spec ification of lin 1.2, 1.3, 2.0 and 2.1. the differences between lin specificati on 1.2 and 1.3 is mainly the physical layer specification. the reason was to improve the compatib ility between the nodes. the lin specification 2.0 is a super set of the 1.3 versio n. the 2.0 version offers new features. however, it is possible to use the lin 1.3 slave node in a 2.0 node cluster, as long as the new features are not used. vice versa it is possible to use a lin 2.0 node in the 1.3 cluster without using the new features. in terms of the physical layer the lin 2.1 specification doesn?t include any changes and is fully compliant to the lin specification 2.0. lin 2.1 is the latest version of the lin specification, released in december 2006.
tle7259g general product characteristics data sheet 13 rev 2.1, 2007-04-27 5 general product characteristics 5.1 absolute maximum ratings note: maximum ratings are absolute ratings; exceeding an y one of these values may cause irreversible damage to the integrated circuit. table 3 absolute maximum ratings voltages, currents and temperatures 1) t j =-40 c to 150 c; all voltages with respect to ground; positive current flowing into pin; (unless otherwise specified) 1) not subject to production test specified by design pos. parameter symbol lim it values unit remarks min. max. voltages 5.1.1 battery supply voltage v s -0.3 40 v lin spec 2.1 param. 10 5.1.2 bus input voltage versus gnd versus v s v bus,g v bus,vs -40 -40 40 40 v v t < 1 s 5.1.3 wake input versus gnd wake input versus v s v wk,g v wk,vs -40 -40 40 40 v v ? 5.1.4 logic voltages at en, txd, rxd v logic -0.3 5.5 v ? 5.1.5 inhibit voltage versus gnd versus v s v inh,g v inh, vs -0.3 -40 40 0,3 v v currents 5.1.6 output current at inh i inh -150 80 ma 2) 2) output current is internally limited to -150 ma temperatures 5.1.7 junction temperature t j -40 150 c? 5.1.8 storage temperature t s -55 150 c? table 4 absolute maximum ratings esd resistivity 1) 1) not subject to production test specified by design pos. parameter symbol lim it values unit remarks min. max. 5.1.9 electrostatic di scharge voltage at v s , bus, wk versus gnd v esd -6 6 kv human body model 2) (100 pf via 1.5 k ? ) 2) esd susceptibility hbm according to eia / jesd 22-a 114b 5.1.10 electrostatic discharge voltage execpt v s versus bus v esd -2 2 kv human body model 2) (100 pf via 1.5 k ? ) 5.1.11 electrostatic di scharge voltage at bus versus v s v esd -1 1 kv human body model (100 pf via 1.5 k ? ) 2)
data sheet 14 rev 2.1, 2007-04-27 tle7259g general product characteristics 5.2 functional range 5.3 thermal resistance 5.4 electrical characteristics table 5 operating range pos. parameter symbol limit values unit remarks min. max. 5.2.1 supply voltage range v s v s 6 40 v lin spec 2.1 param. 10 thermal parameters 5.2.2 junction temperature t j -40 150 c 1) 1) not subject to production test, specified by design table 6 thermal resistance 1) 1) not subject to production test, specified by design pos. parameter symbol limit values unit remarks min. max. 5.3.1 junction to ambient r thja ?185k/w 2) 2) jesd 51-2, 51-3, fr4 76,2 mm x 114,3 mm x 1,5 mm, 70 m, cu, minimal footprint, t a = 27c table 7 electrical characteristics 7.0 v < v s < 27 v; r l = 500 ? ; v en > v en,on ; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max. current consumption 5.4.1 current consumption at v s in recessive state i s,rec 0.1 0.8 1.5 ma recessive state, without r l ; v txd = v cc 5.4.2 current consumption at v s in dominant state i s,dom 0.1 1.3 2.5 ma dominant state, without r l ; v txd = 0 v 5.4.3 current consumption in sleep mode i s,sleep 1?14 a sleep mode, v wk = v s ; v bus = v s 5.4.4 current consumption in sleep mode i s,sleep,typ 1?8 a sleep mode, t j =85c v wk = v s ; v bus = v s 5.4.5 current consumption in stand-by mode i s,stby 0.1 ? 1.5 ma stand-by mode, v wk = v s ; v bus = v s 5.4.6 current consumption in sleep mode, bus shorted to ground i s,sleep,short 51060 a sleep mode, v wk = v s ; v bus = 0v
tle7259g general product characteristics data sheet 15 rev 2.1, 2007-04-27 reset levels 5.4.7 blocking undervoltage detection at v s v s,uv,blk 5 ? 6 communication blocked (see figure 7 ) 5.4.8 power on reset v s,uv,pon ? 2.4 4 v device reset to stand-by- mode (see figure 7 ) 5.4.9 blanking time power on reset detection t blank,uv ?10?s 1) thermal shutdown (junction temperature) 5.4.10 thermal shutdown temp. t jsd 150 170 190 c 1) 5.4.11 thermal shutdown temp. ? t ?10?k 1) receiver output rxd 5.4.12 high level leakage current i rd,h -5 0 5 a v rxd = 5 v; v bus = v s 5.4.13 low level output current i rd,l 1.3 ? 10 ma v rxd = 0.9 v; v bus = 0 v transmission input txd 5.4.14 high level input voltage threshold v td,h ? ? 0.7 v en v recessive state 3.0 v < v en < 5.5 v 5.4.15 txd input hysteresis v td,hys ?0.12 v en ?mv3.0v < v en < 5.5 v 5.4.16 low level input voltage threshold v td,l 0.3 v en ? ? v dominant state 3.0 v < v en < 5.5 v 5.4.17 txd pull-down resistance r td 100 350 800 k ? v txd = 5 v 5.4.18 txd low level leakage current wake = v s i td -1 ? 10 a v en = 0 v; v txd = 0 v v bus = v s 5.4.19 txd dominant current wake = 0 v; v s = 12 v; standby mode i td,l 1.5 3 6 ma v txd = 0.9 v v bus = v s enable input en 5.4.20 high level input voltage threshold v en,on 0.95 ? 2 v normal mode see figure 6 5.4.21 low level input voltage threshold v en,off 0.8 ? 1.85 v low power mode see figure 6 5.4.22 en input hysteresis v en,hys 150 300 450 mv ? 5.4.23 en pull-down resistance r en 15 30 60 k ? ? 5.4.24 enable inhibit high current i en, hc 50 ? 400 a v en = 5 v, 3 v table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v en > v en,on ; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
data sheet 16 rev 2.1, 2007-04-27 tle7259g general product characteristics inhibit output inh 5.4.25 inhibit r on resistance r inh,on 22 36 50 ? i inh = -15 ma 5.4.26 maximum inh output current i inh -150 ? -40 ma v inh = 0 v 5.4.27 leakage current i inh,lk -5.0 ? 5.0 a sleep mode; v inh = 0 v wake input wk 5.4.28 high level input voltage v wk,h v s - 1 ? v s + 3 v ? 5.4.29 low level input voltage v wk,l -0.3 ? v s -3.3 v v? 5.4.30 pull-up current i wk,pu -60 -30 -3 a? 5.4.31 high level leakage current i wk,l -5 ? 5 a v s = 0 v; v wk = 40 v 5.4.32 dominant time for wake-up t wk 30 ? 150 s? bus receiver 5.4.33 receiver threshold voltage, recessive to dominant edge v th,rd 0.4 x v s 0.48 v s ?v? 5.4.34 receiver dominant state v busdom 0 ? 0.4 x v s v lin spec 2.1 param. 17 5.4.35 receiver threshold voltage, dominant to recessive edge v th,dr ?0.52 v s 0.6 x v s v v bus,rec < v bus < 27 v 5.4.36 receiver recessive state v busrec 0.6 x v s ?v s v lin spec 2.1 param. 18 5.4.37 receiver center voltage v bus_cnt 0.475 v s 0.5 v s 0.525 v s v lin spec 2.1 param. 19 5.4.38 receiver hysteresis v hys 0.02 v s 0.04 v s 0.1 v s v lin spec 2.1 param. 20 2) 5.4.39 wake-up threshold voltage v bus,wk 0.40 v s 0.5 v s 0.6 v s v? 5.4.40 dominant time for bus wake-up t wk,bus 30 ? 150 s? table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v en > v en,on ; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
tle7259g general product characteristics data sheet 17 rev 2.1, 2007-04-27 bus transmitter 5.4.41 bus recessive output voltage v bus,ro 0.8 v s ? v s v v txd = high level 5.4.42 bus dominant output voltage maximum load v bus,do 0.6 0.8 ? ? ? 1.2 0.2 x v s 2.0 v v txd = 0 v; r l = 500 ? ; 6.0 v v s 7.3 v 7.3 v < v s 10 v 10 v < v s 18 v 5.4.43 bus dominant output voltage minimum load v bus,do 0.6 0.8 ? ? 1.2 2.0 v v txd = 0 v; r l = 1000 ? ; v s = 7.3 v; v s = 18 v; 5.4.44 bus short circuit current i bus_lim 40 100 150 ma v bus = 13.5 v; lin spec 2.1 param. 12 5.4.45 leakage current i bus_no_gnd -500 -70 0 a v s = 0 v; v bus = -12v; lin spec 2.1 param. 15 5.4.46 leakage current i bus_no_bat ?58 a v s = 0 v; v bus = 18 v; lin spec 2.1 param. 16 5.4.47 leakage current i bus_pas_dom -1 ? ? ma v s = 18 v; v bus = 0 v; lin spec 2.1 param. 13 5.4.48 leakage current i bus_pas_rec ??20 a v s = 8 v; v bus = 18 v; lin spec 2.1 param. 14 5.4.49 bus pull-up resistance r slave 20 30 47 k ? normal mode lin spec 2.1 param. 26 5.4.50 lin output current i bus -60 -30 -5 a sleep mode v s = 12v; en = 0v table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v en > v en,on ; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
data sheet 18 rev 2.1, 2007-04-27 tle7259g general product characteristics dynamic transceiver characteristics 5.4.51 slew rate falling edge t fslope -3 ? -1 v/ s 3) 60% > v bus > 40%; 1 s < ( = r l c bus ) < 5 s; v s = 13.5 v; normal mode; 5.4.52 slew rate rising edge t rslope 1?3v/ s 3) 40% < v bus < 60%; 1 s < ( = r l c bus ) < 5 s; v s = 13.5 v; normal mode; 5.4.53 slope symmetry t slopesym -5 ? 5 s t fslope - t rslope ; v s = 13.5 v; 5.4.54 propagation delay txd low to bus t d(l),t 0.1 1 4 s v en = 5 v; 5.4.55 propagation delay txd high to bus t d(h),t 0.1 1 4 s v en = 5 v; 5.4.56 propagation delay bus dominant to rxd low t d(l),r 0.1 1 6 s v cc = 5 v; c rxd = 20 pf; r rxd = 2.4 k ? ; 5.4.57 propagation delay bus recessive to rxd high t d(h),r 0.1 1 6 s v cc = 5 v; c rxd = 20 pf; r rxd = 2.4 k ? ; 5.4.58 receiver delay symmetry t sym,r -2 ? 2 s t sym,r = t d(l),r - t d(h),r ; 5.4.59 transmitter delay symmetry t sym,t -2 ? 2 s t sym,t = t d(l),t - t d(h),t 5.4.60 delay time for change sleep/stand by mode - normal mode t snorm 0.1 ? 10 s? 5.4.61 delay time for change normal mode - sleep mode t nsleep 0.1 ? 10 s? 5.4.62 txd dominant time out t timeout 6 1220ms v txd = 0 v 5.4.63 txd dominant time out recovery time t torec 1510 s 1) table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v en > v en,on ; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
tle7259g general product characteristics data sheet 19 rev 2.1, 2007-04-27 5.4.64 duty cycle d1 (for worst case at 20 kbit/s) t duty1 0.396 ? ? duty cycle 1 3) th rec (max) = 0.744 v s; th dom (max) =0.581 v s ; v s = 7.0 ? 18 v; t bit = 50 s; d1 = t bus_rec(min) /2 t bit ; lin spec 2.1 param. 27 5.4.65 duty cycle d2 (for worst case at 20 kbit/s) t duty2 ? ? 0.581 duty cycle 2 3) th rec (max) = 0.422 v s ; th dom (max) = 0.284 v s v s = 7.6 ? 18 v; t bit = 50 s; d2 = t bus_rec(max) /2 t bit ; lin spec 2.1 param. 28 1) not subject to production test, specified by design 2) v hys = v busrec - v busdom 3) bus load concerning lin spec 2.1 load 1 = 1 nf / 1 k ? = c bus / r bus load 2 = 6.8 nf / 660 ? = c bus / r bus load 3 = 10 nf / 500 ? = c bus / r bus table 7 electrical characteristics (cont?d) 7.0 v < v s < 27 v; r l = 500 ? ; v en > v en,on ; -40 c < t j < 125 c; all voltages with respect to ground; positive current flowing into pin; unless otherwise specified. pos. parameter symbol limit values unit remarks min. typ. max.
data sheet 20 rev 2.1, 2007-04-27 tle7259g diagrams 6diagrams figure 8 test circuits figure 9 timing diagrams for dynamic ch aracteristics according to lin 1.3 gnd bus r l en rxd 100 nf v s c bus inh txd wk v c c rxd r rxd w g/5 w w g/75 w g+5 w g+75 9 %xvgu *1' 9 %xv 9 6 w g/7 w *1' 9 7[' 9 && w g+7 9 %xvug 9 5[' $(769* w *1' [ 9 && [ 9 && 9 &&
tle7259g diagrams data sheet 21 rev 2.1, 2007-04-27 figure 10 timing diagrams for duty cycl e measurements according to lin 2.1 w %lw w %lw w %lw w %xvbgrppd[ w %xvbuhfplq 7kuhvkrogvri uhfhlylqjqrgh 7kuhvkrogvri uhfhlylqjqrgh 7+ 5hfpd[ 7+ 'rppd[ 7+ 5hfplq 7+ 'rpplq w %xvbgrpplq w %xvbuhfpd[ w u[bsgi w u[bsgu w u[bsgi w u[bsgu 9 683 7udqvfhlyhuvxsso\ riwudqvplwwlqj qrgh 7[' lqsxwwr wudqvplwwlqjqrgh 5[' rxwsxwriuhfhlylqj qrgh 5[' rxwsxwriuhfhlylqj qrgh
data sheet 22 rev 2.1, 2007-04-27 tle7259g application information 7 application information 7.1 esd robustness acco rding to iec61000-4-2 test for esd robustness according to iec61000-4-2 ?gun test? (150 pf, 330 ? ) have been performed. the results and test conditions are available in a seperate test report. 7.2 master termination to achieve the required timings for the dominant to recess ive transition of the bus signal an additional external termination resistor of 1 k ? is mandatory. it is recommended to place this resistor at the master node. to avoid reverse currents from the bus line into the battery supply lin e it is recommended to place a diode in series with the external pull-up. for small systems (low bus capacitance ) the emc performance of the system is supported by an additional capacitor of at least 1 nf in the master node (see figure 11 and figure 12 , application circuit). 7.3 external capacitors a capacitor of 22 f at the supply voltage input v s buffers the input voltage. in combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. the 100 nf capacitors close to the v s pins of the tle7259g and the volt age regulator help to improve the emc behavior of the system. table 8 esd ?gun test? performed test result unit remarks electrostatic discharge voltage at pin v s , bus, wk versus gnd +8 kv 1) positive pulse 1) esd susceptibility ?esd gun? according lin emc 1.3 test spec ification, section 4. 3. (iec 61000-4-2) -tested by external testhouse (ibee zwickau, emc testreport nr. 16-05-06). electrostatic discharge voltage at pin v s , bus, wk versus gnd -8 kv 1) negative pulse
tle7259g application information data sheet 23 rev 2.1, 2007-04-27 7.4 application example figure 11 application circuit with bu s short to gnd feature applied ecu 1 txd gnd tle7259 bus 100 nf c gnd master node wk inh v s e. g. tle4263 v q 5 v gnd inh 100 nf 22 f 22 f v i 1 k ? 1 nf 100 nf rxd en v c ecu x aea03511.vsd txd gnd tle7259 bus c gnd slave node wk inh 100 nf v s 22 f rxd en v bat lin bus v c e. g. tle4263 gnd inh v i 5 v v q 220 pf 100 nf 22 f 100 nf
data sheet 24 rev 2.1, 2007-04-27 tle7259g application information figure 12 application circuit without bus short to gnd feature ecu 1 txd gnd tle 7259 bus c gnd wk inh 100 nf 1 k ? v s 1 nf e. g. tle 4263 v q 5 v gnd inh 22 f v i rxd en v c master node v bat lin bus ecu x aea03512new.vsd txd gnd tle 7259 bus c gnd slave node wk inh v s 5 v 22 f e. g. tle 4263 v q gnd inh v i v s rxd en v c 220 pf 100 nf 100 nf 22 f 100 nf 100 nf 100 nf 22 f
tle7259g package outlines data sheet 25 rev 2.1, 2007-04-27 8 package outlines figure 13 p-dso-8 (plastic dual small outline) does not include plastic or metal protrusion of 0.15 max. per side -0.05 -0.2 +0.1 5 0.41 index marking (chamfer) x8 1 1) 4 8 1.27 5 a 0.1 0.2 m a (1.5) 0.1 min. 1.75 max. c c 6 ?.2 0.64 0.33 4 -0.2 -0.0 1 0.2 +0.05 x 45? ?.08 1) ?.25 max. 8? 1) index marking gps09032 f or further information on alternativ e packages, please visit our website: h ttp://www.infine on.com/packages dimensions in mm
data sheet 26 rev 2.1, 2007-04-27 tle7259g revision history 9 revision history version date changes rev 2.0 2006-07-19 creation of data sheet rev. 2.1 2007-04-30 changes are described in a sepe rate delta sheet for tle7259g revision 1.0
edition 2007-04-27 published by infineon technologies ag 81726 munich, germany ? 2007 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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